module MainDec (
    input [5:0] Op,
    output MemtoReg, MemWrite,
    output Branch, ALUSrc,
    output RegDst, RegWrite,
    output Jump,
    output [1:0] ALUOp);

    reg [8:0] Controls;

    assign {RegWrite, RegDst, ALUSrc, Branch, MemWrite, MemtoReg, Jump, ALUOp} = Controls;

    always@(*)
        case(Op)
            6'b000000: Controls <= 9'b110000010; // RTYPE (add, sub, and, or, slt)
            6'b000011: Controls <= 9'b010101000; // LW (Load Word)
            6'b100101: Controls <= 9'b001010000; // SW (Store Word)
            6'b001100: Controls <= 9'b000100001; // BEQ (Branch Equal)
            6'b001000: Controls <= 9'b010000000; // ADDI (Add Immediate)
            6'b001111: Controls <= 9'b010000011; // LUI (Load Upper Immediate) - NEW!
            6'b000010: Controls <= 9'b000000100; // J (Jump)
            default:   Controls <= 9'bxxxxxxxxxx; // Illegal Op
        endcase
endmodule